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general description the max16826 high-brightness led (hb led) driver is designed for backlighting automotive lcd displays and other display applications such as industrial or desktop monitors and lcd televisions. the max16826 integrates a switching regulator controller, a 4-channel linear cur- rent sink driver, an analog-to-digital converter (adc), and an i 2 c interface. the ic is designed to withstand automotive load dump transients up to 40v and can operate under cold crank conditions. the max16826 contains a current-mode pwm switching regulator controller that regulates the output voltage to the led array. the switching regulator section is config- urable as a boost or sepic converter and its switching frequency is programmable from 100khz to 1mhz. the max16826 includes 4 channels of programmable, fault-protected, constant-current sink driver controllers that are able to drive all white, rgb, or rgb plus amber led configurations. led dimming control for each chan- nel is implemented by direct pwm signals for each of the four linear current sinks. an internal adc measures the drain voltage of the external driver transistors and the output of the switching regulator. these measurements are then made available through the i 2 c interface to an external microcontroller (c) to enable output voltage optimization and fault monitoring of the leds. the amplitude of the led current in each linear current- sink channel and the switch-mode regulator output volt- age is programmed using the i 2 c interface. additional features include: cycle-by-cycle current limit, shorted led string protection, and overtemperature protection. the max16826 is available in a thermally enhanced, 5mm x 5mm, 32-pin thin qfn package and is specified over the automotive -40c to +125c temperature range. applications lcd backlighting: automotive infotainment displays automotive cluster displays industrial and desktop monitors lcd tvs automotive lighting: adaptive front lighting low- and high-beam assemblies features external mosfets allow wide-range led current with multiple leds per string individual pwm dimming inputs per string very wide dimming range led string short and open protection adjustable led current rise/fall times improve emi control microcontroller interface using i 2 c allows led voltage monitoring and optimization using a 7-bit internal adc led short and open detection dynamic adjustment of led string currents and output voltage standby mode integrated boost/sepic controller external switching frequency synchronization 4.75v to 24v operating voltage range and withstands 40v load dump overvoltage and overtemperature protection max16826 programmable, four-string hb led driver with output-voltage optimization and fault detection ________________________________________________________________ maxim integrated products 1 ordering information 19-4047; rev 3; 6 /10 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. evaluation kit available part temp range pin-package MAX16826ATJ+ - 40c to + 125c 32 tqfn-ep* MAX16826ATJ/v+ - 40c to + 125c 32 tqfn-ep* typical application circuit and pin configuration appear at end of data sheet. + denotes a lead(pb)-free/rohs-compliant package. * ep = exposed pad. /v denotes an automotive qualified part. simplified diagram max16826 dr4 dr1 dl1 in dl boost led driver cs fb gnd v in dim1 dim2 sda scl dim3 dim4 i 2 c interface dimming inputs cs1 dl4 cs4 ordering information continued at end of data sheet.
max16826 programmable, four-string hb led driver with output-voltage optimization and fault detection 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v in = 12v, r19 = 2k , c33 = 2200pf, r17 = 1.27k , c dl_ = 0.01?, t j = -40? to +125?, unless otherwise noted. typical values are at t a = +25?.) (note 1) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. in to gnd (continuous) .........................................-0.3v to +30v in peak current ( 400ms) ...............................................300ma in continuous current ........................................................50ma pgnd to gnd .......................................................-0.3v to +0.3v all other pins to gnd...............................................-0.3v to +6v dl peak current (< 100ns)....................................................?a dl continuous current .....................................................?0ma dl1, dl2, dl3, dl4 peak current ..................................?0ma dl1, dl2, dl3, dl4 continuous current ........................?0ma v cc continuous current .....................................................50ma all other pins current .......................................................?0ma continuous power dissipation (t a = +70?) 32-pin thin qfn (derate 34.5mw/? above +70?) multilayer board ..........................................................2759mw operating temperature range .........................-40? to +125? junction temperature ......................................................+150? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) ........?300? soldering temperature (reflow) .......................................+260? parameter symbol conditions min typ max units power-supply voltage v in v sync = 3v 4.75 24 v quiescent current i in dl_ = unconnected; r19, c33 = open 5 10 ma shutdown current i in,sd v sync = 0v 20 75 ? standby current i in,sb i 2 c standby activated 3 ma i 2 c-compatible i/o (scl, sda) input high voltage v ih 1.5 v input low voltage v il 0.5 v input hysteresis v hys 25 mv input high leakage current i ih v logic = 5v -1 +1 ? input low leakage current i il v logic = 0v -1 +1 ? input capacitance c in 10 pf output low voltage v ol i ol = 3ma 0.4 v output high current i oh v oh = 5v 1 a i 2 c-compatible timing serial clock (scl) frequency f scl 400 khz bus free time between stop and start conditions t buf 1.3 ? start condition hold time t hd:sta 0.6 ? stop condition setup time t su:sto 0.6 ? clock low period t low 1.3 ? clock high period t high 0.6 ? data setup time t su:dat 0.3 ? data in hold time t hd:datin 0.03 0.9 ? data out hold time t hd:datout 0.3 ?
max16826 programmable, four-string hb led driver with output-voltage optimization and fault detection _______________________________________________________________________________________ 3 parameter symbol conditions min typ max units maximum receive scl/sda rise time t r c b = 400pf 300 ns minimum receive scl/sda rise time t r c b = 400pf 60 ns maximum receive scl/sda fall time t f c b = 400pf 300 ns minimum receive scl/sda fall time t f c b = 400pf 60 ns transmit sda fall time t f c b = 400pf, i o = 3ma 60 250 ns pulse width of suppressed spike t sp 50 ns internal regulators (in, v cc ) v cc output voltage v vcc 0v < i vcc < 30ma (note 2), 4.75v < v in < 24v, dl, dl1 to dl4 unconnected 4.5 5.25 5.65 v v cc undervoltage lockout v vcc_uvlo v cc rising 4.5 v v cc undervoltage lockout hysteresis v vcc_hys 135 175 205 mv in shunt regulation voltage i in = 250ma 24.05 26.0 27.5 v pwm gate driver (dl) peak source current 2a peak sink current 2a dl high-side driver resistance i dl = -100ma 2.25 dl low-side driver resistance i dl = +100ma 1.30 minimum dl pulse width 40 ns pwm controller, soft-start (fb, comp, ovp) fb shorted to comp; max16826 only 1.230 1.250 1.260 fb voltage maximum v fb,max fb shorted to comp; max16826b only 1.23 1.25 1.27 v fb shorted to comp; max16826 only 862 876 885 fb voltage minimum v fb,min fb shorted to comp; max16826b only 735 750 765 mv fb shorted to comp; max16826 only 2.94 fb voltage lsb fb shorted to comp; max16826b only 3.9 mv fb input bias current i fb 0v < v fb < 5.5v -100 0 +100 na feedback-voltage line regulation level to produce v comp = 1.25v, 4.5v < v vcc < 5.5v ?.25 %/v soft-start current i ss v css = 0.5v vcc 3.2 6.0 10.4 ? ovp input bias current i ovp 0v < v ovp < 5.5v -100 0 +100 na slope compensation i slope 19 26 32 ?/? electrical characteristics (continued) (v in = 12v, r19 = 2k , c33 = 2200pf, r17 = 1.27k , c dl_ = 0.01?, t j = -40? to +125?, unless otherwise noted. typical values are at t a = +25?.) (note 1)
max16826 programmable, four-string hb led driver with output-voltage optimization and fault detection 4 _______________________________________________________________________________________ parameter symbol conditions min typ max units error amplifier (fb, comp) open-loop gain a ol 80 db unity-gain bandwidth bw 2 mhz phase margin pm 65 degrees sourcing, v comp = 3v 1.9 error-amplifier output current i comp sinking, v comp = 2v 0.9 ma comp clamp voltage v comp v fb = 0v 3.25 4.5 v comp short-circuit current i comp_sc 12 ma pwm current limit (cs) cycle-by-cycle current-limit threshold v cl v dl = 0v 187 200 217 mv cycle-by-cycle current-limit propagation time to dl t prop, cl 10mv overdrive 80 ns gross current-limit threshold v gcl v css = 0v 250 270 280 mv gross current-limit propagation time to dl t prop,gcl 10mv overdrive 80 ns input bias current 0v < v cs < 5.5v -100 0 +100 na pwm oscillator (rtct) rtct voltage ramp (peak to peak) v ramp 5.5v < v in < 24v 1.60 1.65 1.80 v rtct voltage ramp valley v ramp_valley 5.5v < v in < 24v 1.11 1.20 1.27 v discharge current i dis v rtct = 2v 7.8 8.4 9.1 ma frequency range f osc 5.5v < v in < 24v 100 1000 khz synchronization (sync/enable) input rise/fall time 200 ns input frequency range 100 1000 khz input high voltage 1.5 v input low voltage 0.5 v input minimum pulse width 200 ns input bias current 0v < v sync < 5.5v -100 0 +100 na delay to shutdown v sync = 0v 13 32 65 ? led dimming (dim1?im4) input high voltage v dim,max 1.5 v input low voltage v dim,min 0.5 v minimum dimming frequency f dim t on = 2? (note 3) 45 hz input bias current i dim 0v < v dim_ < 5.5v -100 0 +100 na electrical characteristics (continued) (v in = 12v, r19 = 2k , c33 = 2200pf, r17 = 1.27k , c dl_ = 0.01?, t j = -40? to +125?, unless otherwise noted. typical values are at t a = +25?.) (note 1)
max16826 programmable, four-string hb led driver with output-voltage optimization and fault detection _______________________________________________________________________________________ 5 parameter symbol conditions min typ max units adc (dr1?r4, ovp) maximum error e max ?0 mv adc single bit acquisition latency (note 4) 2 s dr channel sample time t dr,smpl 190 ms ovp channel sample time t ovp,smpl 20 ? full-scale input voltage v fs 1.215 1.24 1.2550 v least significant bit v lsb 9.76 mv dr input bias current i dr 0v < v dr_ < 5.5v -100 0 +100 na drain fault comparators (dr1?r4) (shorted led string comparator) drain fault comparator threshold v dfth voltage to drive dl1?l4 low 1.4 1.52 1.63 v drain fault comparator delay t dfd 10mv overdrive 1 s linear regulators (dl1?l4, cs1?s4) transconductance gm i = -500? 75 ms maximum output current i dl sourcing or sinking 15 ma cs1?s4 input bias current i cs 0v < v cs < 5.5v -100 0 +100 na cs_ = dl_, fb dac full scale; max16826 only 306 316 324 cs1?s4 regulation voltage maximum v cs,max cs_ = dl_, fb dac full scale; max16826b only 308 318 328 mv cs_ = dl_, fb dac minus full scale; max16826 only 90 97 105 cs1?s4 regulation voltage minimum v cs,min cs_ = dl_, fb dac minus full scale; max16826b only 90 99 109 mv cs1?s4 regulation voltage lsb v cs,lsb cs_ = dl_, fb dac 1-bit transition 1.72 mv electrical characteristics (continued) (v in = 12v, r19 = 2k , c33 = 2200pf, r17 = 1.27k , c dl_ = 0.01?, t j = -40? to +125?, unless otherwise noted. typical values are at t a = +25?.) (note 1) note 1: all devices are 100% production tested at t j = +25? and t j = +125?. limits to -40? are guaranteed by design. note 2: i cc includes the internal bias currents and the current used by the gate drivers to drive dl, dl1, dl2, dl3, and dl4. note 3: minimum frequency to allow the internal adc to complete at least one measurement. t on is the on-time with the led current in regulation. note 4: minimum led current pulse duration, which is required to correctly acquire 1 bit.
max16826 programmable, four-string hb led driver with output-voltage optimization and fault detection 6 _______________________________________________________________________________________ supply current vs. supply voltage max16826 toc01 supply voltage (v) supply current (ma) 20 16 4 8 12 2 4 6 8 10 12 14 16 0 024 c dl = 4700pf supply current vs. oscillator frequency max16826 toc02 oscillator frequency (khz) supply current (ma) 900 800 700 600 500 400 300 200 10 20 30 40 0 100 1000 c dl = 4700pf c33 from 680pf to 8200pf supply current vs. temperature max16826 toc03 temperature ( c) supply current (ma) 110 85 60 35 10 -15 13 14 15 16 17 12 -40 c dl = 4700pf oscillator frequency vs. supply voltage max16826 toc04 supply voltage (v) oscillator frequency (khz) 20.3 16.6 12.9 9.2 310 320 330 340 350 360 300 5.5 24.0 oscillator frequency vs. temperature max16826 toc05 temperature ( c) oscillator frequency (khz) 110 85 60 35 10 -15 240 280 320 360 400 200 -40 led output current vs. temperature max16826 toc06 temperature ( c) led output current (ma) 80 60 40 20 137 139 141 143 145 135 0100 v cs = 0.32v typical operating characteristics (v in = 12v, r19 = 2k ? , c33 = 2200pf, r17 = 1.27k ? , c dl_ = 0.01f. t a = +25c, unless otherwise noted.) led output current vs. input voltage max16826 toc07 input voltage (v) led output current (ma) 18 12 6 30 60 90 120 150 0 024 dim input to iled output waveform max16826 toc08 2 s/div 5v/div 100ma/div 0ma 0v v dim i led
max16826 programmable, four-string hb led driver with output-voltage optimization and fault detection _______________________________________________________________________________________ 7 enable and disable response max16826 toc09 40ms/div 5v/div 100ma/div 0ma 0v v sync/en i led v cc voltage vs. load current max16826 toc10 load current (ma) v cc voltage (v) 40 30 20 10 5.1 5.2 5.3 5.4 5.5 5.0 050 v cc voltage vs. temperature max16826 toc11 temperature ( c) v cc voltage (v) 80 60 40 20 5.1 5.2 5.3 5.4 5.5 5.0 0100 typical operating characteristics (continued) (v in = 12v, r19 = 2k ? , c33 = 2200pf, r17 = 1.27k ? , c dl_ = 0.01f. t a = +25c, unless otherwise noted.) v cc voltage vs. supply voltage max16826 toc12 supply voltage (v) v cc voltage (v) 20 16 12 8 4 1 2 3 4 5 6 0 024 shunt voltage vs. shunt current max16826 toc13 shunt current (ma) shunt voltage (v) 200 150 100 50 24.5 25.0 25.5 26.0 26.5 27.0 24.0 0250 shunt voltage vs. temperature max16826 toc14 temperature ( c) shunt voltage (v) 110 85 60 35 10 -15 23 24 25 26 27 28 22 -40 shunt regulator load dump response max16826 toc15 200ms/div 20v/div 10v/div 0v 0v v supply v shunt
max16826 programmable, four-string hb led driver with output-voltage optimization and fault detection 8 _______________________________________________________________________________________ pin description pin name function 1 pgnd power ground 2, 3 gnd analog ground 4 rtct timing resistor and capacitor connection. a resistor, r19 (in the typical application circuit ), from v cc to rtct and a capacitor c33, from rtct to gnd set the oscillator frequency. see the oscillator section to calculate rt and ct component values. 5 sync/en synchronization and enable input. there are three operating modes: sync/en = low: low current shutdown mode with all circuits shut down except shunt regulator. sync/en = high: all circuits active with oscillator frequency set by rtct network. sync/en = clocked: all circuits active with oscillator frequency set by sync clock input. conversion cycles initiate on the rising edge of external clock input. the frequency programmed by r19/c33 must be 10% lower than the input sync/en signal frequency. 6 css soft-start timing capacitor connection. connect a capacitor from css to gnd to program the required soft- start time for the switching regulator output voltage to reach regulation. see the soft-start (css) section to calculate c css . 7 comp switching regulator compensation component connection. connect the compensation network between comp and fb. 8fb switching regulator feedback input. connect fb to the center of a resistor-divider connected between the switching regulator output and gnd to set the output voltage. fb is regulated to a voltage set by an internal register. see the setting output voltage section for calculating resistor values. 9 ovp switching regulator overvoltage input. connect ovp to the center of a resistor-divider connected between the switching regulator output and gnd. for normal operation, configure the resistor-divider so that the voltage at this pin does not exceed 1.25v. if operation under load dump conditions is also required, configure the resistor- divider so that the voltage at ovp is less than 1.25v. 10 rsc slope compensation resistor and pwm comparator input connection. connect a resistor, r17, from rsc to the switching current-sense resistor to set the amount of the compensation ramp. see the slope compensation (rsc) section for calculating the value. 11 sda i 2 c serial data input/output 12 scl i 2 c serial clock input 13 dim1 led string 1 logic-level pwm dimming input. a high logic level on dim1 enables the current sink to operate at the maximum current as determined by its sense resistor and internal register value. a low logic level disables the current source. 14 dim2 led string 2 logic-level pwm dimming input. a high logic level on dim2 enables the current sink to operate at the maximum current as determined by its sense resistor and internal register value. a low logic level disables the current source. 15 dim3 led string 3 logic-level pwm dimming input. a high logic level on dim3 enables the current sink to operate at the maximum current as determined by its sense resistor and internal register value. a low logic level disables the current source. 16 dim4 led string 4 logic-level pwm dimming input. a high logic level on dim4 enables the current sink to operate at the maximum current as determined by its sense resistor and internal register value. a low logic level disables the current source. 17 cs1 led string 1 current-sense input. cs1 is regulated to a value set by an internal register. the regulation voltage can be set between 97mv and 316mv.
max16826 programmable, four-string hb led driver with output-voltage optimization and fault detection _______________________________________________________________________________________ 9 pin description (continued) pin name function 18 dl1 le d s tr i ng 1 li near c ur r ent s our ce o utp ut. d l1 d r i ves the g ate of the exter nal fe t on le d s tr i ng 1 and has ap p r oxi m atel y 15m a sour ce/si nk cap ab i l i ty. c onnect a m i ni m um cap aci tor of 4700p f fr om d l1 to g n d to com p ensate the i nter nal tr anscond uctance am p l i fi er as w el l as p r og r am the r i se and fal l ti m es of the le d cur r ents. 19 dr1 led string 1 external fet drain voltage sense. the internal adc uses this input to measure the drain to gnd voltage of the current sink fet. drain voltage measurement information can be read back from the i 2 c interface. connect a voltage-divider to scale drain voltage as necessary. 20 cs2 led string 2 current-sense input. cs2 is regulated to a value set by an internal register. the regulation voltage can be set between 97mv and 316mv. 21 dl2 led string 2 linear current source output. dl2 drives the gate of the external fet on led string 2 and has approximately 15ma source/sink capability. connect a minimum capacitor of 4700pf from dl2 to gnd to compensate the internal transconductance amplifier, as well as program the rise and fall times of the led currents. 22 dr2 led string 2 external fet drain voltage sense. the internal adc uses this input to measure the drain to gnd voltage of the current sink fet. drain voltage measurement information can be read back from the i 2 c interface. connect a voltage-divider to scale drain voltage as necessary. 23 cs3 led string 3 current-sense input. cs3 is regulated to a value set by an internal register. the regulation voltage can be set between 97mv and 316mv. 24 dl3 le d s tr i ng 3 li near c ur r ent s our ce o utp ut. d l3 d r i ves the g ate of the exter nal fe t on le d s tr i ng 3 and has ap p r oxi m atel y 15m a sour ce/si nk cap ab i l i ty. c onnect a m i ni m um cap aci tor of 4700p f fr om d l3 to g n d to com p ensate the i nter nal tr anscond uctance am p l i fi er , as w el l as p r og r am the r i se and fal l ti m es of the le d cur r ents. 25 dr3 led string 3 external fet drain voltage sense. the internal adc uses this input to measure the drain to gnd voltage of the current sink fet. drain voltage measurement information can be read back from the i 2 c interface. connect a voltage-divider to scale drain voltage as necessary. 26 cs4 led string 4 current-sense input. cs4 is regulated to a value set by an internal register. the regulation voltage can be set between 97mv and 316mv. 27 dl4 le d s tr i ng 4 li near c ur r ent s our ce o utp ut. d l3 d r i ves the g ate of the exter nal fe t on le d s tr i ng 4 and has ap p r oxi m atel y 15m a sour ce/si nk cap ab i l i ty. c onnect a m i ni m um cap aci tor of 4700p f fr om d l4 to g n d to com p ensate the i nter nal tr anscond uctance am p l i fi er , as w el l as p r og r am the r i se and fal l ti m es of the le d cur r ents. 28 dr4 led string 4 external fet drain voltage sense. the internal adc uses this input to measure the drain to gnd voltage of the current sink fet. drain voltage measurement information can be read back from the i 2 c interface. connect a voltage-divider to scale drain voltage as necessary. 29 in power supply. in is internally connected to a 26v shunt regulator that sinks current. in conjunction with an external resistor it allows time-limited load dump events as high as 40v to be safely handled by the ic. bypass in to gnd with a minimum 10f capacitor. 30 cs current-sense input 31 v cc gate driver regulator output. bypass v cc to gnd with a minimum 4.7f ceramic capacitor. gate drive current pulses come from the capacitor connected to v cc . place the capacitor as close as possible to v cc . if in is powered by a voltage less than 5.5v, connect v cc directly to in. 32 dl switching regulator gate driver output ep exposed pad. connect the exposed pad to the ground plane for heatsinking. do not use this pad as the only ground connection to the ic.
detailed description the max16826 hb led driver integrates a switching regulator controller, a 4-channel linear current sink dri- ver, a 7-bit adc, and an i 2 c interface. the ic is designed to operate from a 4.75v to 24v input voltage range and can withstand automotive load dump tran- sients up to 40v. the current-mode switching regulator controller is con- figurable as a boost or sepic converter to regulate the voltage to drive the four strings of hb leds. its program- mable switching frequency (100khz to 1mhz) allows the use of a small inductor and filter capacitors. the four current sink regulators use independent external current- sense resistors to provide constant currents for each string of leds. four dim inputs allow a very wide range of independent pulsed dimming to each led string. an internal 7-bit adc measures the drain voltage of the external driver transistors to enable output voltage opti- mization and fault monitoring of the leds. the max16826 is capable of driving four strings of leds. the number of leds in each string is only limited by the topology of choice, the rating of the external compo- nents, and the resolution of the adc and internal dac. simplified block diagram 31 in 5v v cc v cc pgnd dl cs ovp comp fb rtct gnd ovt current- mode pwm block sync/en css dr4 7-bit adc and shorted string fault dectection dr3 dr2 dr1 linear current- sink drivers cs4 cs3 cs2 cs1 dl4 dl3 dl2 dl1 i 2 c state machine double- buffered register and dacs dim4 dim3 ovt ovt dim2 dim1 sda scl 26v shunt gnd ovt ref v cc gnd rsc max16826 29 28 25 22 19 26 23 20 17 27 24 21 18 16 15 14 13 9 32 1 30 8 10 6 7 4 5 2 3 11 12 max16826 programmable, four-string hb led driver with output-voltage optimization and fault detection 10 ______________________________________________________________________________________
the max16826 provides additional flexibility with an internal i 2 c serial interface to communicate with a microcontroller (c). the interface can be used to dynamically adjust the amplitude of the led current in each led string and the switch-mode regulator output voltage. it can also be used to read the adc drain volt- age measurements for each string, allowing a c to dynamically adjust the output voltage to minimize the power dissipation in the led current sink fets. the i 2 c interface can also be used to detect faults such as led short or open. modes of operation the max16826 has six modes of operation: normal mode, undervoltage lockout (uvlo) mode, thermal shutdown (tsd) mode, shutdown (shdn) mode, standby (stby) mode, and overvoltage protection (ovp) mode. the normal mode is the default state where each cur- rent sink regulator is maintaining a constant current through each of the led strings. digitized voltage feed- back from the drains of the current sink fets can be used to establish a secondary control loop by using an external c to control the output of the switching stage for the purpose of achieving low-power dissipation across these fets. uvlo mode occurs when v vcc goes below 4.3v. in uvlo mode, each of the linear current sinks and the switching regulator is shut down until the input voltage exceeds the rising uvlo threshold. tsd mode occurs when the die temperature exceeds the internally set thermal limit (+160c). in tsd mode, each of the linear regulators and the switching regulator is shut down until the die temperature cools by 20c. shdn mode occurs when sync/en is driven low. in shdn mode, all internal circuitry with the exception of the shunt regulator is deactivated to limit current draw to less than 50a. shdn mode disengages when sync/en is driven high or clocked. stby mode is initiated using the i 2 c interface. in stby mode, each of the linear current sinks and the switching regulator is shut down. stby mode is also deactivated using the i 2 c interface. in stby mode, the internal v cc regulator and the shunt regulator remain active. whenever the max16826 enters a mode that deactivates the switch- ing regulator, the soft-start capacitor is discharged so that soft-start occurs upon reactivation. ovp mode occurs when the voltage at ovp is higher than the internal reference. in ovp mode, the switching regula- tor gate-drive output is latched off and can only be restored by cycling enable, power, or entering standby mode. switching preregulator stage the max16826 features a current-mode controller that is capable of operating in the frequency range of 100khz to 1mhz. current-mode control provides fast response and simplifies loop compensation. output voltage regulation can be achieved in a two- loop configuration. a required conventional control loop can be set up by using the internal error amplifier with its inverting input connected to fb. the bandwidth of this loop is set to be as high as possible utilizing con- ventional compensation techniques. the noninverting input of this amplifier is connected to a reference volt- age that is dynamically adjustable using the i 2 c inter- face. the optional slower secondary loop consists of the external c using the i 2 c interface reading out the voltages at the drains of the current sink fets and adjusting the reference voltage for the error amplifier. to regulate the output voltage, the error amplifier com- pares the voltage at fb to the internal 1.25v (adjustable down by using the i 2 c interface) reference. the output of the error amplifier is compared to the sum of the cur- rent-sense signal and the slope compensation ramp at rsc to control the duty cycle at dl. two current-limit comparators also monitor the voltage across the sense resistor using cs. if the primary cur- rent-limit threshold is reached, the fet is turned off and remains off for the reminder of the switching cycle. if the current through the fet reaches the secondary cur- rent limit, the switching cycle is terminated and the soft- start capacitor is discharged. the converter then restarts in soft-start mode preventing inductor current runaway due to the delay of the primary cycle-by-cycle current limit. the switching regulator controller also fea- tures an overvoltage protection circuit that latches the gate driver off if the voltage at ovp exceeds the inter- nal 1.25v reference voltage. max16826 programmable, four-string hb led driver with output-voltage optimization and fault detection ______________________________________________________________________________________ 11
max16826 shunt regulator the max16826 has an internal 26v (typ) shunt regula- tor to provide the primary protection against an auto- motive load dump. when the input voltage is below 26v, the shunt voltage at in tracks the input voltage. when the input voltage exceeds 26v, the shunt regula- tor turns on to sink current, and the voltage at in is clamped to 26v. during a load dump, the input voltage can reach 40v, and the shunt regulator through the resistor connected to in is forced to sink large amounts of current for up to 400ms to limit the voltage that appears at in to the shunt regulation voltage. the sink- ing current of the shunt regulator is limited by the value of resistor (r1 in figure 1) in series with in. there are two criteria that determine the value of r1: the maxi- mum acceptable shunt current during load dump, and the voltage drop on r1 under normal operating condi- tions with low battery voltage. for example, with typical 20ma input current in normal operation, 250ma load dump current limit, 40v maximum load dump voltage, the r1 value is: where v inmin is the minimum operating voltage and v inreg is the minimum acceptable voltage at in. use the following equation to verify that the current through r1 is less than 250ma under a load-dump con- dition: for stable operation, the shunt regulator requires a min- imum 10f of ceramic capacitance from in to gnd. v cc regulator the 5.25v v cc regulator provides bias for the internal circuitry including the bandgap reference and gate dri- vers. externally bypass v cc with a minimum 4.7f ceramic capacitor. v cc has the ability to supply up to 50ma of current, but external loads should be mini- mized so as not to take away drive capability for inter- nal circuitry. if in is powered by a voltage less than 5.5v, connect v cc directly to in. switch-mode controller the max16826 consists of a current-mode controller that is capable of operating in the 100khz to 1mhz fre- quency range (figure 2). current-mode control pro- vides fast response and simplifies loop compensation. the error amplifier compares the voltage at fb to 1.25v and varies the comp output accordingly to regulate. the pwm comparator compares the voltage at comp with the voltage at rsc to determine the switching duty cycle. the primary cycle-by-cycle current-limit com- parator interrupts the on-time if the sense voltage is larger than 200mv. when the sense voltage is larger than 270mv, the secondary gross current-limit com- parator is activated to discharge the soft-start capaci- tor. this forces the ic to re-soft-start preventing inductor current runaway due to the delay of the prima- ry cycle-by-cycle current limit. the switch-mode controller also features a low current shutdown mode, adjustable soft-start, and thermal shutdown protection. i vv r ma ld ld === ?? 26 1 40 26 100 140 r vv i inmin inreg q 1 75 55 20 10 100 3 == = ?? ? .. ? programmable, four-string hb led driver with output-voltage optimization and fault detection 12 ______________________________________________________________________________________ max16826 5v reference + - r1 in v in c4 figure 1. shunt regulator block diagram
max16826 programmable, four-string hb led driver with output-voltage optimization and fault detection ______________________________________________________________________________________ 13 ovp css fb swr dac i 2 c bus q q set clr s r q q set clr s r 6 a 1.25v comp shdn stby oscillator 26 a/ s sync rtct rsc soft-start comparator ovp comparator error amplifier pwm comparator dl cs 270mv 200mv v cc 10 a max16826 current- ramp generator v cc current-limit comparators - - + + - + - + - + - + analog mux figure 2. switch regulator controller block diagram
max16826 programmable, four-string hb led driver with output-voltage optimization and fault detection 14 ______________________________________________________________________________________ oscillator the max16826 oscillator frequency is programmable using an external capacitor (c33 in the typical application circuit ) and a resistor (r19) at rtct. r19 is connected from rtct to v cc and c33 is connected from rtct to gnd. c33 charges through rt until v rtct reaches 2.85v. ct then discharges through an 8.4ma internal current sink until v rtct drops to 1.2v. c33 is then allowed to charge through r19 again. the period of the oscillator is the sum of the charge and discharge times of c3. calculate these times as follows: the charge time is: t c = 0.55 x r19 x c33 the discharge time is: where t c and t d is in seconds, r19 is in ohms ( ? ), and c33 is in farads (f). the oscillator frequency is then: the charge time (t c ) in relation to the period (t c + t d ) sets the maximum duty cycle of the switching regulator. therefore, the charge time (t c ) is constrained by the desired maximum duty cycle. typically, the duty cycle should be limited to 95%. the oscillator frequency is programmable from 100khz to 1mhz. the max16826 can be synchronized to an external oscillator through sync/en. slope compensation (rsc) the max16826 uses an internal ramp generator for slope compensation to stabilize the current loop when the duty cycle exceeds 50%. a slope compensation resistor (r17 in the typical application circuit ) is con- nected between rsc and the switching current-sense resistor at the source of the external switching fet. when the voltage at dl transitions from low to high, a ramped current with a slope of 26a/s is generated and flows through the slope compensation resistor. it is effectively summed with the current-sense signal. when the voltage at dl is low, the current ramp is reset to 0. calculate r17 as follows: where v out is the switching regulator output and v inmin is the minimum operating input voltage. current limit (cs) the max16826 includes a primary cycle-by-cycle, cur- rent-limit comparator and a secondary gross current- limit comparator to terminate the on-time or switch cycle during an overload or fault condition. the current- sense resistor (r12 in the typical application circuit ) connected between the source of the switching fet and gnd and the internal threshold, set the current limit. the current-sense input (cs) has a voltage trip level (v cs ) of 200mv. use the following equation to cal- culate r39: r12 = v cs /i pk where i pk is the peak current that flows through the switching fet. when the voltage across r12 exceeds the current-limit comparator threshold, the fet driver (dl) turns the switch off within 80ns. in some cases, a small rc filter may be required to filter out the leading- edge spike on the sensed waveform. set the time con- stant of the rc filter at approximately 100ns and adjust as needed. if, for any reason, the voltage at cs exceeds the 270mv trip level of the gross current limit as set by a second comparator, then the switching cycle is immediately terminated and the soft-start capacitor is discharged. this allows a new soft-start cycle and prevents inductor current buildup. soft-start (css) soft-start is achieved by charging the external soft-start capacitor (c30 in the typical application circuit ) at startup. an internal fixed 6a current source charges the soft-start capacitor until v css reaches v cc . to achieve the required soft-start timing for the switching regulator output voltage to reach regulation, the value of the soft-start capacitor at css is calculated as: c30 = 6a x t ss /v ref where t ss is the required time to achieve the switching regulator output regulation and v ref is the set fb regu- lation voltage. when the ic is disabled, the soft-start capacitor is discharged to gnd. synchronization and enable input the sync/en input provides both external clock syn- chronization (if desired) and enable control. when sync/en is held low, all circuits are disabled and the ic enters low-current shutdown mode. when sync/en is high, the ic is enabled and the switching regulator clock uses the rtct network to set the operating fre- quency. see the oscillator section for details. the sync/en can also be used for frequency synchroniza- tion by connecting it to an external clock signal from 100khz to 1mhz. the switching cycle initiates on the r vv r l out inmin 17 12 34 28 1 = ? () . f tt osc cd = + 1 tr c r r d = () ?? ln . . 19 33 19 281 86 19 487 4 45 () ()
rising edge of the clock. when using external synchro- nization, the clock frequency set by rtct must be 10% lower than the synchronization signal frequency. overvoltage protection (ovp) ovp limits the maximum voltage of the switching regu- lator output for protection against overvoltage due to circuit faults, for example a disconnected fb. connect ovp to the center of a resistor-divider connected between the switching regulator output and gnd to set the output-voltage ovp limit. typically, the ovp output voltage limit is set higher than the load dump voltage. calculate the value of r15 and r16 as follows: r15 = (v ovp /1.25 - 1) x r16 or to calculate v ovp : v ovp = 1.25 x (1 + r15/r16) where r15 and r16 are shown in the typical application circuit . the internal ovp comparator compares the volt- age at ovp with the internal reference (1.25v typ) to decide if an overvoltage error occurs. if an overvoltage error is detected, switching stops, the switching regula- tor gate-drive output is latched off, and the soft-start capacitor is discharged. the latch can only be reset by toggling sync/en, activating the i 2 c standby mode, or cycling power. the internal adc also uses ovp to sense the switching regulator output voltage. output voltage measurement information can be read back from the i 2 c interface. voltage is digitized to 7-bit resolution. undervoltage lockout (uvlo) when the voltage at v cc is below the v cc undervolt- age threshold (v vcc_uvlo , typically 4.3v falling), the max16826 enters undervoltage lockout. v cc uvlo forces the linear regulators and the switching regulator into shutdown mode until the v cc voltage is high enough to allow the device to operate normally. in v cc uvlo, the v cc regulator remains active. thermal shutdown the max16826 contains an internal temperature sensor that turns off all outputs when the die temperature exceeds +160c. the outputs are enabled again when the die temperature drops below +140c. in thermal shutdown, all internal circuitry is shut down with the exception of the shunt regulator. linear current sources (cs1?s4, dl1?l4) the max16826 uses transconductance amplifiers to con- trol each led current sink. the amplifier outputs (dl1Cdl4) drive the gates of the external current sink fets (q2 to q5 in the typical application circuit ). the source of each mosfet is connected to gnd through a current- sense resistor. cs1Ccs4 are connected to the respective inverting input of the amplifiers and also to the source of the external current sink fets where the led string cur- rent-sense resistors are connected. the noninverting input of each amplifier is connected to the output of an internal dac. the dac output is programmable using the i 2 c inter- face to output between 97mv and 316mv. the regulated string currents are set by the value of the current-sense resistors (r28 to r31 in the typical application circuit ) and the corresponding dac output voltages. led pwm dimming (dim1?im4) the max16826 features a versatile dimming scheme for controlling the brightness of the four led strings. independent led string dimming is accomplished by dri- ving the appropriate dim1Cdim4 inputs with a pwm sig- nal with a frequency up to 100khz. although the brightness of the corresponding led string is proportional to the duty cycle of its respective pwm dimming signal, finite led current rise and fall times limit this linearity when the dim pulse width approaches 2s. each led string can be independently controlled. simultaneous control of the pwm dimming and the led string currents in an ana- log way over a 3:1 range provides great flexibility allowing independent two-dimensional brightness control that can be used for color point setup and brightness control. analog-to-digital converter (adc) the max16826 has an internal adc that measures the drain voltage of the external current sink driver fets (q2 to q5 in the typical application circuit ) using dr1 - dr4 and the switching regulator output voltage using ovp. fault monitoring and switching stage out- put-voltage optimization is possible by using an exter- nal microcontroller to read out these digitized voltages through the i 2 c interface. the adc is a 7-bit sar (suc- cessive-approximation register) topology. it sequential- ly samples and converts the drain voltage of each channel and v ovp . an internal 5-channel analog mux is used to select the channel the adc is sampling. conversions are driven by an internally generated 1mhz clock and gated by the external dimming sig- nals. after a conversion, each measurement is stored into its respective register and can be accessed through the i 2 c interface. the digital circuitry that con- trols the analog mux includes a 190ms timer. if the adc does not complete a conversion within this 190ms measurement window then the analog mux will sequence to the next channel. for the adc to complete one full conversion, the cumulative pwm dimming on- time must be greater than 10s within the 190ms mea- surement window. the minimum pwm dimming on-time max16826 programmable, four-string hb led driver with output-voltage optimization and fault detection ______________________________________________________________________________________ 15
max16826 is 2s, so the adc requires at least 5 of these minimum pulses within the 190ms measurement window to com- plete a conversion. during pwm dimming, led current pulse widths of less than 2s are possible, but the adc may not have enough sampling time to complete a con- version in this scenario and the corresponding data may be incomplete or inaccurate. therefore, adaptive volt- age optimization may not be possible when the led current-pulse duration is less than 2s. the led current pulse duration is shorter than the pulse applied at the dim_ inputs because of the led turn-on delay. faults and fault detection the max16826 features circuitry that automatically detects faults such as overvoltage or shorted led string. an internal fault register at the address oah is used to record these faults. for example, if a shorted led string is detected, the corresponding fault register bit is set and the faulty output is shut down. shorted led strings are detected with fast comparators connected to dr1Cdr4. the trip threshold of these comparators is 1.52v (typ). when this threshold is exceeded, the shorted string is latched off and the cor- responding bit of register oah is set. after the internal adc completes a conversion, the result is stored in the corresponding register and can be read out by the external c. the c then compares the conversion data with the preset limit to determine if there is a fault. when an led string opens, the voltage at the corre- sponding current-sink fet drain node goes to 0v. however, the adc can only complete a conversion if the led current comes into regulation. if an led string opens before the led current can come into regulation, the adc cannot complete a conversion and the msb (eighth bit) is set to indicate an incomplete conversion or timeout condition. thus, an examination of the msb provides an indication that the led string is open. if the led string opens after the led current is in regulation, the adc can make conversions and reports that the drain voltage is 0v. therefore, to detect an open condi- tion, monitor the msb and the adc measurement. if the msb is set and the cs_ on-time is greater than 2s, or if the adc measures 0 at the drain, then there is an open circuit. programmable, four-string hb led driver with output-voltage optimization and fault detection 16 ______________________________________________________________________________________ table 1. adc response condition adc response shorted string fault load full-scale code into register, no conversions on affected channel until power or enable is cycled. shorted string fault while converting immediately load full-scale code into register and cease conversion effort on this channel until power or enable is cycled. adc register read when it is being updated previous sample is shifted out through the i 2 c interface and then the register is updated with the new measurement. uvlo immediately terminate conversions, do not update current register. stby immediately terminate conversions, do not update current register. shdn immediately terminate conversions, do not update current register. register file unit adc dac power management ovp i 2 c system clock external events figure 3. digital block diagram
overview of the digital section figure 3 shows the block diagram of the digital section in the max16826. the i 2 c serial interface provides flexible control of the ic and is in charge of writing/reading to/from the register file unit. the adc block is a 7-bit 5-channel sar adc. the eighth bit of the adc data reg- ister indicates an incomplete conversion or timeout has occurred. this bit is set whenever the led current fails to come into regulation during the dim pwm on-time. this indicates there is either an led open condition or the cs_ on-time is less than 2s. a reason for this among other possibilities is an open led string condition. this eighth or msb bit can be tested to determine open string faults. i 2 c interface the max16826 internal i 2 c serial interface provides flexible control of the amplitude of the led current in each string and the switch-mode regulator output volt- age. it is also able to read the current sink fet drain voltages, as well as the switching regulator output volt- age through ovp and thus enable some fault detection and power dissipation minimization. by using an exter- nal c, the max16826 internal control and status regis- ters are also accessed through the standard bidirectional, 2-wire, i 2 c serial interface. the i 2 c interface provides the following i/o functions and programmability: ? current sink fet drain and switching regulator out- put-voltage measurement. the measurement for each channel and the regulator output is stored in its respective register and can be accessed through the i 2 c interface. the sar adc measures the drain voltage of each current sink fet sequen- tially. this uses one 8-bit register for each channel to store the measurement made by the 7-bit sar adc and 1 bit to indicate a timeout during the adc conversion cycle. ? adjustment of the switching regulator output. this is used for adaptive voltage optimization to improve overall efficiency. the switching regulator output is downward adjustable by changing its reference voltage. this uses a 7-bit register. ? adjustment of the reference voltage of the current- sink regulators. the reference voltage at the nonin- verting input of each of the linear regulator drive amplifiers can be changed to make adjustments in the current of each led string for a given sense resistor. the output can be adjusted down from a maximum of 316mv to 97mv in 1.72mv increments. ? fault reporting. when a shorted string fault or an overvoltage fault occurs, the fault is recorded. ? standby mode. when a one is entered into the standby register the ic goes into standby mode. the 7-bit i 2 c address is 58h and the 8-bit i 2 c address is b1h for a read operation and b0h for a write opera- tion. address the max16826 using the i 2 c interface to read the state of the registers or to write to the registers. upon a read command, the max16826 transmits the data in the register that the address register is pointing to. this is done so that the user has the ability to confirm the data written to a register before the output is enabled. use the fault register to diagnose any faults. serial addressing the i 2 c interface consists of a serial data line (sda) and a serial clock line (scl) to achieve bidirectional communication between the master and the slave. the max16826 is a slave-only device, relying upon a mas- ter to generate a clock signal. the master initiates data transfer to and from the max16826 and generates scl to synchronize the data transfer (figure 4). max16826 programmable, four-string hb led driver with output-voltage optimization and fault detection ______________________________________________________________________________________ 17 scl sda t r t f t buf start condition stop condition repeated start condition start condition t su,sto t hd,sta t su,sta t hd,dat t su,dat t low t high t hd,sta figure 4. 2-wire serial interface timing detail
max16826 i 2 c is an open-drain bus. both sda and scl are bidi- rectional lines, connected to a positive supply voltage using a pullup resistor. they both have schmitt triggers and filter circuits to suppress noise spikes on the bus to ensure proper device operation. a bus master initiates communication with the max16826 as a slave device by issuing a start con- dition followed by the max16826 address. the max16826 address byte consists of 7 address bits and a read/write bit (r/ w ). after receiving the proper address, the max16826 issues an acknowledge bit by pulling sda low during the ninth clock cycle. start and stop conditions both scl and sda remain high when the bus is not busy. the master signals the beginning of a transmis- sion with a start (s) condition by transitioning sda from high to low while scl is high. when the master has finished communicating with the max16826, it issues a stop (p) condition by transitioning sda from low to high while scl is high. the bus is then free for another transmission (figure 4). both start and stop conditions are generated by the bus master. bit transfer each data bit, from the most significant bit to the least significant bit, is transferred one by one during each clock cycle. during data transfer, the sda signal is allowed to change only during the low period of the scl clock and it must remain stable during the high period of the scl clock (figure 5). acknowledge the acknowledge bit is used by the recipient to hand- shake the receipt of each byte of data (figure 6). after data transfer, the master generates the acknowledge clock pulse and the recipient pulls down the sda line during this acknowledge clock pulse, such that the sda line stays low during the high duration of the clock pulse. when the master transmits the data to the max16826, it releases the sda line and the max16826 takes the control of sda line and generates the acknowledge bit. when sda remains high during this 9th clock pulse, this is defined as the not acknowledge signal. the master then generates either a stop condi- tion to abort the transfer, or a repeated start condi- tion to start a new transfer. programmable, four-string hb led driver with output-voltage optimization and fault detection 18 ______________________________________________________________________________________ start condition (s) data line stable data valid data allowed to change stop condition (p) scl sda figure 5. bit transfer scl sda by master 1 289 s start condition clock pulse for acknowledgment sda by slave figure 6. acknowledge
accessing the max16826 the communication between the c and the max16826 is based on the usage of a set of protocols defined on top of the standard i 2 c protocol definition. they are exclusively write byte(s) and read byte(s). write byte(s) the write byte protocol is as follows: 1) the master sends a start condition. 2) the master sends the 7-bit slave address followed by a write bit (low). 3) the addressed slave asserts an ack by pulling sda low. 4) the master sends an 8-bit command code. 5) the slave asserts an ack by pulling sda low. 6) the master sends an 8-bit data byte. 7) the slave acknowledges the data byte. 8) the master generates a stop condition or repeats 6 and 7 to write next byte(s). the command is interpreted as the destination address (register file unit) and data is written in the addressed location. the slave asserts a nack at step 5 if the com- mand is not valid. the master then interrupts the com- munication by issuing a stop condition. if the address is correct, the data byte is written to the addressed reg- ister. after the write, the internal address pointer is increased by one. when the last location is reached, it cycles to the first register. read byte(s) the read sequence is: 1) the master sends a start condition. 2) the master sends the 7-bit slave address plus a write bit (low). 3) the addressed slave asserts an ack on the data line. 4) the master sends an 8-bit command byte. 5) the active slave asserts an ack on the data line. 6) the master sends a repeated start condition. 7) the master sends the 7-bit slave address plus a read bit (high). 8) the addressed slave asserts an ack on the data line. 9) the slave sends an 8-bit data byte. 10) the master asserts a nack on the data line to complete operations or asserts an ack and repeats 9 and 10. 11) the master generates a stop condition. the data byte read from the device is the content of the addressed location(s). once the read is done, the inter- nal pointer is increased by one. when the last location is reached, it cycles to the first one. if the device is busy or the address is not correct (out of memory map), the command code is not acknowledged and the internal address pointer is not altered. the master then inter- rupts the communication by issuing a stop condition. max16826 programmable, four-string hb led driver with output-voltage optimization and fault detection ______________________________________________________________________________________ 19 s ack slave address r/w 7 bits 0 command 8 bits ack ack p data command byte: select register to write data byte data goes into the register set by the command byte 8 bits write byte format figure 7. write byte format s ack slave address r/w 7 bits 0 ack slave address r/w 7 bits 1 command 8 bits ack sr nack p data command byte: prepare device for following read data byte data comes from the register set by the command byte 8 bits read byte format figure 8. read byte format
max16826 register file unit the register file unit is used to store all the control infor- mation from the sda line and configure the max16826 for different operating conditions. the register file assignments of the max16826 are in table 2. registers 00h to 03h: string current programming these registers are used to program led string 1 to led string 4 current sink values. for each led string, cs1Ccs4 inputs are connected to the source of the external current sink fet and internally are connected to the inverting input of the internal transconductance amplifier. the noninverting input of this amplifier is con- nected to the output of an internal dac programmed by these registers. as the dac is incremented, its out- put voltage decreases from 316mv to 97mv in 1.72mv steps by the data written in the register 00h to 03h; thus, the steady-state voltage at cs1Ccs4 is given by the following formula: v cs1,2,3,4 = 316mv - (1.72mv x registervalue[6:0]) for example, if 00h is set to 20h, then the cs1 voltage is: v cs1 = 316mv - 1.72mv x 32 = 265.3mv register 04h: switching regulator output programming set the switching regulator output voltage by connect- ing fb to the center of a resistive voltage-divider between the switching regulator output and gnd. v fb is regulated to a voltage from 876mv to 1.25v (typ) set by the register 04h through the i 2 c interface. the fb reference voltage can be decreased from 1.25v, its maximum value, by approximately 2.9mv steps. the steady-state voltage at fb then is regulated to: v fb = 1.25v - (2.91mv x 04h[6:0]) registers 05h to 08h: external current-sink fet drain voltage adc readings these registers store the drain voltages of the external current sink fets. for each register, bits 6C0 are the conversion data of the adc outputs. bit 7 is used to show if the conversion is terminated by the adc (indi- cated by 0) or if there is an internal timeout (indicated by 1). if the drain voltage exceeds the preset reference voltage, the corresponding led string fault bit is assert- ed. see the faults and fault detection section for more information on the internal timeout function. register 09h: switching regulator voltage adc output bits 6-0 of this register store the voltage present at ovp. this voltage is a scaled down version of the switching regulator output voltage. bit 7 is not used. register 0ah: fault status register this register stores all the external events or fault infor- mation such as overvoltage and shorted led string faults. the fault events are logged only if the system is not in standby mode and their active states are longer than one clock cycle. cycle enable or power to clear the fault status register. initiating standby mode using the i 2 c interface can also be used to clear the fault status programmable, four-string hb led driver with output-voltage optimization and fault detection 20 ______________________________________________________________________________________ table 2. register file assignments register address r/w used bit range reset value description 00h r/w [6:0] 00h led string 1 current programming value. 01h r/w [6:0] 00h led string 2 current programming value. 02h r/w [6:0] 00h led string 3 current programming value. 03h r/w [6:0] 00h led string 4 current programming value. 04h r/w [6:0] 00h switching regulator output voltage programming value. 05h r [7:0] 00h led string 1 external fet drain voltage adc output. 06h r [7:0] 00h led string 2 external fet drain voltage adc output. 07h r [7:0] 00h led string 3 external fet drain voltage adc output. 08h r [7:0] 00h led string 4 external fet drain voltage adc output. 09h r [6:0] 00h ovp voltage, adc output. 0ah r [5:0] 00h fault status register. 0bh r/w [0] 00h device standby command. 0ch r [2:0] device revision code.
register. first, activate standby mode and then deacti- vate this mode using the i 2 c interface. next, perform a read operation on the fault status register. the old fault information is reported in this first read operation. the conclusion of the read operation clears the data con- tained in the register. subsequent read operations con- firm that the fault status register has been cleared. the description of this register is as follows: bit 0: overvoltage sense flag. this flag is set if the volt- age at ovp exceeds 1.25v; switching stops until power or the enable or standby is cycled. ? bit 1: not used. ? bit 2: led string 1 shorted flag. a diode short in led string 1 has been detected if this bit is set. ? bit 3: led string 2 shorted flag. a diode short in led string 2 has been detected if this bit is set. ? bit 4: led string 3 shorted flag. a diode short in led string 3 has been detected if this bit is set. ? bit 5: led string 4 shorted flag. a diode short in led string 4 has been detected if this bit is set. register 0bh bit 0: device standby command when register 0bh bit 0 is set to 1, the ic enters a low- current standby mode. in this mode, the system clock is off and no operation is allowed. set this bit to 0 to leave standby mode and back to normal operation mode. register 0ch bit 2-0: device revision code these 3 bits are a hardwired value that identifies the ics revision. applications information programming led currents the max16826 uses sense resistors (r28, r29, r30, r31 in the typical application circuit ) to set the output current for each led string. to set the led current for a particular string, connect a sense resistor across the corresponding current-sense input (cs1Ccs4) and gnd. for optimal accuracy, connect the low-side of the current-sense resistors to gnd with short traces. the value needed for the sense resistor for a given current is calculated with the equation below: r31 = v cs1 /i out1 where v cs1 can be set from 97mv to 316mv by the internal registers through the i 2 c interface and i out1 is the desired led string 1 current. calculating the value of peak current-limit resistor the value of r12 sets the peak switching current that flows in the switching fet (q1). set the value of resistor r12 using the equation below: r12 = 0.19/(1.2 x i pk ) where i pk is the peak inductor current at minimum input voltage and maximum load. boost inductor value the value of the boost inductor is calculated using the following equation: where v inmin is the minimum input voltage, v out is the desired output voltage, and f sw is the switching fre- quency, and ? i l is the peak-to-peak ripple in the boost inductor. higher inductor values lead to lower ripple but at a higher cost and size. choose an inductor value that gives peak-to-peak ripple current in the order of 30% to 40% of the average current in the inductor at low-line and full-rated load. this choice of inductor is a compromise between cost, size, and performance for the boost converter. setting output voltage set the switch regulator output voltage by connecting fb to the center of a resistive voltage-divider between the switching regulator output and gnd. v fb is regulat- ed to a voltage from 0.88v to 1.25v (typ) set by an internal register through the i 2 c interface. choose r13 and r14 in the typical application circuit for a reason- able bias current in the resistive divider and use the fol- lowing formula to set the output voltage: v out = (1 + r13/r14) x v fb where v fb is the regulated voltage set by the internal register. adaptive voltage optimization the availability of the digitized switching regulator output voltage and current sink drain voltages and the ability to change the switching regulator output voltage provide the ability to do adaptive voltage optimization. a slow digital control loop is established with an external c closing the loop. firmware residing in the external c is tasked to read each one of the current sink fet drain voltages and select the minimum value of the four led strings. the minimum value is subtracted from the scaled output voltage reading, and then the switching regulator output is forced to maintain the difference required to provide current regulation in the current sink fets. l1 v vv v f i inmin out inmin oswl = () ? ut ? max16826 programmable, four-string hb led driver with output-voltage optimization and fault detection ______________________________________________________________________________________ 21
max16826 sepic topology the sepic power topology is very useful when the input voltage is expected to be higher or lower than the output voltage of the switching regulator stage as required by the number of leds used in a single string. the sepic topology is more complex than the simple boost topology and it requires the use of two additional energy storage components, l2 and c25, in figure 9. programmable, four-string hb led driver with output-voltage optimization and fault detection 22 ______________________________________________________________________________________ max16826 q2 r26 r28 c41 r21 r23 r25 r27 q1 r12 r17 q3 r24 r29 c42 q4 r22 r30 c43 q5 r20 r18 c29 r31 cs1 dl1 c44 gnd gnd pgnd gnd gnd gnd v cc r19 gnd rtct gnd gnd gnd css cs4 c33 c32 dl4 cs3 dl3 cs2 dl2 dr1 dr2 dr3 dr4 c30 gnd gnd d1 l2 gnd c27 ovp fb c25 comp rsc in cs dl dimming inputs system interface r16 r15 gnd r14 r13 gnd r11 v out l1 gnd c26 v in scl i 2 c interface sda sync/en dim4 dim3 dim2 dim1 scl sda enable dim gnd system c gnd c28 r35 r32 r33 r34 figure 9. sepic-based led driver
pcb layout and routing careful pcb layout is important for proper operation. use the following guidelines for good pcb layout: ? minimize the area of the high current-switching loop of the rectifier diode, switching fet, sense resistor, and output capacitor to avoid excessive switching noise. use wide and short traces for the gate-drive loop from dl, to the fet gate, and through the cur- rent-sense resistor, then returning to the ic pgnd and gnd. ? connect high-current input and output components with short and wide connections. the high-current input loop is from the positive terminal of the input capacitor to the inductor, to the switching fet, to the current-sense resistor, and to the negative ter- minal of the input capacitor. the high-current output loop is from the positive terminal of the input capac- itor to the inductor, to the rectifier diode, to the posi- tive terminal of the output capacitor, reconnecting between the output capacitor and input capacitor ground terminals. avoid using vias in the high-cur- rent paths. if vias are unavoidable, use multiple vias in parallel to reduce resistance and inductance. ? place the feedback and even voltage-divider resis- tors as close to fb and ovp as possible. the divider center trace should be kept short. placing the resistors far away causes the sensing trace to become antennas that can pick up switching noise. avoid running the sensing traces near drain con- nection of the switching fet. ? place the input bypass capacitor as close to the device as possible. the ground connection of the bypass capacitor should be connected directly to gnd with a wide trace. ? minimize the size of the switching fet drain node while keeping it wide and short. keep the drain node away from the feedback node and ground. if possible, avoid running this node from one side of the pcb to the other. use dc traces as shields, if necessary. ? provide large enough cooling copper traces for the external current sink fets. calculate the worst-case power dissipation and allocate sufficient area for cooling. ? refer to the max16826 evaluation kit for an exam- ple of proper board layout. max16826 programmable, four-string hb led driver with output-voltage optimization and fault detection ______________________________________________________________________________________ 23
max16826 programmable, four-string hb led driver with output-voltage optimization and fault detection 24 ______________________________________________________________________________________ typical application circuit max16826 q2 r26 r28 c41 r21 r23 r25 r27 q1 r12 r17 q3 r24 r29 c42 q4 r22 r30 c43 q5 r20 r18 c29 r31 cs1 dl1 c44 gnd gnd pgnd gnd gnd gnd v cc r19 gnd rtct gnd gnd gnd css cs4 c33 c32 dl4 cs3 dl3 cs2 dl2 dr1 dr2 dr3 dr4 c30 gnd gnd d1 c28 gnd c27 ovp fb comp rsc in cs dl system interface r16 r15 gnd r14 r13 gnd r11 v out l1 gnd c26 v in (40v load dump ok) scl sda sync/en dim4 dim3 dim2 dim1 scl sda enable dim gnd system c dimming inputs i 2 c interface r35 r32 r33 r34 boost led driver
max16826 programmable, four-string hb led driver with output-voltage optimization and fault detection ______________________________________________________________________________________ 25 chip information process: bicmos max16826 tqfn (5mm x 5mm) top view 29 30 28 27 12 11 13 gnd rtct snyc/en css comp 14 pgnd cs3 dl2 cs2 dl3 dr1 dl1 1 2 dr4 4567 23 24 22 20 19 18 in cs dim2 dim1 scl sda gnd dr2 3 21 31 ep exposed pad. 10 v cc rsc 32 9 dl ovp dl4 26 15 dim3 cs4 25 16 dim4 fb cs1 8 17 dr3 package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages . note that a +, #, or - in the package code indicates rohs status only. package draw- ings may show a different suffix character, but the drawing per- tains to the package regardless of rohs status. package type package code document no. 32 tqfn-ep t3255-4 21-0140 pin configuration ordering information (continued) part temp range pin-package max16826batj+ - 40c to + 125c 32 tqfn-ep* max16826batj/v+ - 40c to + 125c 32 tqfn-ep* + denotes a lead(pb)-free/rohs-compliant package. * ep = exposed pad. /v denotes an automotive qualified part.
max16826 programmable, four-string hb led driver with output-voltage optimization and fault detection maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 26 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2010 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 8/08 initial release 1 3/09 added automotive version, updated features , ec table , typical operating characteristics , switching preregulator stage, oscillator, analog-to-digital (adc), faults and fault detection sections 1, 2, 5, 6, 11, 14?7, 20 2 12/09 improve definition of minimum on-time for proper adc operation 5, 10, 16 3 6/10 added max16826b part 2?, 25

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